Many microcontroller applications involve bus operations which occur entirely within a microcontroller unit (MCU). Such bus operations include read and write operations of internal control registers, internal data registers, and on-chip memory. Such operations are generally not visible to a device external to the microcontroller. However, in a development environment, observability of these internal operations is often required.
Generally, an external bus circuit within the microcontroller unit provides an interface between a fast internal bus of the microcontroller unit and devices external to the microcontroller unit. The external bus circuit is also responsible for external bus management and for accessing the internal bus to multiplex address and data signals on the same integrated circuit terminals at different times during a bus operation. By multiplexing address and data signals on the same integrated circuit terminals, the external bus circuit may reduce a total integrated circuit terminal count of the microcontroller unit and, therefore, provide a low cost data processor.
An attractive feature of the external bus circuit is its ability to enable the microcontroller unit to have a low terminal count. The cost can be drastically affected via the elimination of the data bus terminals. Therefore, all external bus cycles, including show cycles, may be required to use a multiplexed bus interface.
In a development environment, the external bus circuit is also responsible for providing external visibility of internal bus cycles. This is provided to support both passive tools such as logic analyzers and bus analyzers and active tools which require tracking of internal control operations in real time. The mechanism for providing external visibility of internal bus cycles is referred to as a show-cycle and requires a different data bus timing from a standard external bus cycle. In general, the address phase of the show-cycle is similar to a standard external bus cycle wherein a data phase is delayed. The data phase is delayed because valid data from an internal read cycle cannot be driven externally until it is valid internally within the microcontroller unit. The data is not valid internally within the microcontroller until the end of the external bus cycle. Then, there is a delay while the external bus circuit drives data externally. Therefore, the data phase of a standard show read cycle is not provided until the very end of a current bus cycle and actually protrudes into a following bus cycle.
A conventional show cycle mechanism provides show-cycles on a non-multiplexed bus. The conventional show cycle mechanism provides extension of the data phase of a bus cycle into a following bus cycle. In the following bus cycle, a data phase had not begun and the integrated circuit data terminals may be reused until a start of the data phase begins. However, in the case of a multiplexed bus, the following bus cycle requires the use of the same address/data bus integrated circuit terminals to perform an address phase. There is no room in time for the data phase extension of the show cycle. By the time data retrieved during an internal read operation would be valid on the external integrated circuit terminals of the multiplexed bus of the microcontroller, an address from a following bus cycle will be present on the same integrated circuit terminals. In the multiplexed bus example described above, the conventional sequence of a show cycle is inappropriate in this situation. In an emulation mode of operation, the external bus circuit must also provide real time visibility of internal write operations to support external development tools which control synchronization to internal functions.
Show cycles have been used in data processors for years. However, the show-cycles in such data processors are typically provided on a non-multiplexed bus. The conventional show cycle mechanism provides extension of the data phase of a bus cycle into a following bus cycle, for which a data phase of the following bus cycle has not yet begun. Therefore, the integrated circuit data terminals may be reused until the data phase begins. As data processors provide more and more density of function, there is less need for a non-multiplexed external bus. However, due to the physical requirements of the show cycle and due to the physical restraints of the multiplexed address/data bus, current technology cannot provide internal data during the same external bus cycle as the internal cycle.
Additionally, the emulation cycle is used to track the control of internal functions of a data processor through the use of external shadow registers. Some control signals are decoded concurrently with the latched address phase of the multiplexed bus cycle to generate the address of the shadow register. The shadow register is associated with an external synthesis circuit which requires real-time visibility of control changes in order to remain synchronous with internal data processing functions. Typical development tools will exploit this feature to support several individual functions. Each of the functions exhibits the same basic architecture of a shadow register and provides real-time duplication of an internal register which controls an external function that must track the behavior of an internal function in real time. These functions are reliant upon the emulation cycle's provision of internal write visibility in real time.